 | Digital Teaching Aid (DED Philippinen, 86 p.) |
 |  | Counter - Lesson 8 |
| | Lesson Plan |
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Asynchronous counter
Fig. 8-1: Asynchronous counter
with JK-MS-FF in toggle mode
To understand how this counter works lets have a look at the timing diagram:
Fig. 8-2: Timing diagram,
asynchronous mod 8 counter
The frequency of waveform C is one half that at B, but is only one-eighth the clock frequency.
The FF's are negative edge triggered, hence output signals change only at the falling side of the clock pulse.
Fig. 8-3: Truth table, asynchronous mod 8 counter
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CLK transition |
C |
B |
A |
|
0 |
0 |
0 |
0 |
|
1 |
0 |
0 |
1 |
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2 |
0 |
1 |
0 |
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3 |
0 |
1 |
1 |
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4 |
1 |
0 |
0 |
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5 |
1 |
0 |
1 |
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6 |
1 |
1 |
0 |
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7 |
1 |
1 |
1 |
|
0 |
0 |
0 |
0 |
A three Flip-Flop counter is often referred to as a mod 8 (modulus 8) counter since it has 8 states.
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23 = 8 output conditions |
(The exponent equals to the number of Flip-Flops) |
The largest decimal number which is represented by a 3 Flip-Flop counter is:
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23 - 1 = 7 |
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In general: |
2n - 1 |
Count Down mode
Switching the clock inputs of each Flip-Flop to the 
outputs causes the counting sequence to start at 111
down to 000.
HO: How many Flip-Flops are required to construct a mod-128 counter? A mod-32? What is the largest decimal number that can be stored in a mod-64 counter?
Solution:
* mod-128 must have 7 Flip-Flops (27 = 128)
* mod-32 must have 5 Flip-Flops
* mod-64, the largest decimal number is 63
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