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close this bookDigital Teaching Aid (DED Philippinen, 86 p.)
close this folderFlip-Flops - Lesson 7
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View the documentRS Flip-Flops
View the documentD - Flip-Flop (D-FF)
View the documentJK Flip-Flop (JK-FF)

JK Flip-Flop (JK-FF)

Flip - Flops can be used to build counters, JK-FF are the ideal elements for that purpose.


Fig. 7-11: JK-FF, logic circuit

Ex: What is the truth table for the circuit above?

Fig. 7-12: Truth table, JK-FF

CLK

J

K

Q

X

0

0

last state

­

0

1

0

­

1

0

1

­

1

1

toggle

J and K ® low:

Both AND gates are disabled, clock pulses have no effect. Q retains its last value.

J ® low, K ® high:

The upper gate is disabled, only reset is possible (unless Q is already reset).

J ® high, K ® low:

The lower gate is disabled, only set is possible (unless Q is already high).

J and K ® high:

Set or reset is possible, the Flip-Flop will “toggle” on the next positive clock edge. Toggle means to switch to the opposite state.


Fig. 7-13: JK-FF's, logic symbols

Preset (PR) and Clear (CLR) are input signals to get a definite start point.

JK Master-Slave FF (JK-MS-FF)


Fig. 7-14: JK-MS-FF, logic circuit

Regardless what the master does, the slave copies it. The slave copies the master on the negative clock edge. This circuit provides a way to avoid racing.


Fig. 7-15: JK-MS-FF, logic symbol

Available as TTL device: 74 LS 76