![]() | Digital Teaching Aid (DED Philippinen, 86 p.) |
![]() | ![]() | (introduction...) |
![]() | ![]() | Preface |
![]() | ![]() | Introduction |
![]() | ![]() | Fundamental Logic Operations - Lesson 1 |
![]() | ![]() | Lesson Plan |
![]() | ![]() | (introduction...) |
![]() | ![]() | Introduction |
![]() | ![]() | TTL circuits |
![]() | ![]() | Logic operations |
![]() | ![]() | Handout No. 1 |
![]() | ![]() | Worksheet No. 1 |
![]() | ![]() | Introduction Boolean Algebra - Lesson 2 |
![]() | ![]() | Lesson Plan |
![]() | ![]() | Introduction |
![]() | ![]() | Boolean algebra |
![]() | ![]() | Boolean equations of logic circuits |
![]() | ![]() | NOR and NAN gates |
![]() | ![]() | De Morgan's theorems |
![]() | ![]() | Worksheet No. 2 |
![]() | ![]() | Circuit Analysis and Design - Lesson 3 |
![]() | ![]() | Lesson Plan |
![]() | ![]() | (introduction...) |
![]() | ![]() | Introduction |
![]() | ![]() | Boolean laws and theorems |
![]() | ![]() | Sum of product method |
![]() | ![]() | Design example |
![]() | ![]() | Handout No. 2 |
![]() | ![]() | Worksheet No. 3 |
![]() | ![]() | First Evaluation |
![]() | ![]() | Karnaugh Mapping - Lesson 4 |
![]() | ![]() | Lesson Plan |
![]() | ![]() | (introduction...) |
![]() | ![]() | Introduction |
![]() | ![]() | Karnaugh map |
![]() | ![]() | Truth table to Karnaugh map |
![]() | ![]() | Pairs, Quads, and Octets |
![]() | ![]() | Overlapping and Rolling |
![]() | ![]() | Worksheet No. 4 |
![]() | ![]() | Karnaugh Mapping II - Lesson 5 |
![]() | ![]() | Lesson Plan |
![]() | ![]() | (introduction...) |
![]() | ![]() | Introduction |
![]() | ![]() | Product of sums method |
![]() | ![]() | Don't care conditions |
![]() | ![]() | Worksheet No. 5 |
![]() | ![]() | Coding - Lesson 6 |
![]() | ![]() | Lesson Plan |
![]() | ![]() | (introduction...) |
![]() | ![]() | Introduction |
![]() | ![]() | ASCII code |
![]() | ![]() | Excess-3 code |
![]() | ![]() | Gray code |
![]() | ![]() | Encoder |
![]() | ![]() | Decoder |
![]() | ![]() | Code converter |
![]() | ![]() | Worksheet No. 6 |
![]() | ![]() | Flip-Flops - Lesson 7 |
![]() | ![]() | Lesson Plan |
![]() | ![]() | (introduction...) |
![]() | ![]() | Introduction |
![]() | ![]() | RS Flip-Flops |
![]() | ![]() | D - Flip-Flop (D-FF) |
![]() | ![]() | JK Flip-Flop (JK-FF) |
![]() | ![]() | Worksheet No. 7 |
![]() | ![]() | Second Evaluation |
![]() | ![]() | Counter - Lesson 8 |
![]() | ![]() | Lesson Plan |
![]() | ![]() | (introduction...) |
![]() | ![]() | Introduction |
![]() | ![]() | Asynchronous counter |
![]() | ![]() | Synchronous counter |
![]() | ![]() | Seven segment indicator and decoder |
![]() | ![]() | Worksheet No. 8 |
![]() | ![]() | Data Processing Circuits - Lesson 9 |
![]() | ![]() | Lesson Plan |
![]() | ![]() | (introduction...) |
![]() | ![]() | Introduction |
![]() | ![]() | Multiplexer |
![]() | ![]() | Demultiplexer |
![]() | ![]() | Handout No. 3 |
![]() | ![]() | Worksheet No. 9 |
![]() | ![]() | Third Evaluation |
![]() | ![]() | Answers to Evaluation Problems |
No. 1 Draw the logic diagram, truth table, and the waveform for a three flip-flop serial counter that uses JK master slave flip-flops sensitive to positive clock transition.
No. 2 Determine the number of possible states in a counter composed of the following number of flip-flops:
a) 5
b) 8
c) 11
No. 3 Draw the logic diagram, truth table, and waveforms for a two flip-flop serial counter operating in the count down mode.
No. 4 Design the internal logic circuit for the 7448 (seven segment decoder for the common cathode indicator).
No. 5 Sketch the logic circuit for the following seven segment indicators:
a) common cathode type
b) common anode type