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XS - XILINX 2000/3000 FPGA Simulator

Jason Zien, Jackson Kong, Pak K. Chan, Martine Schlag

October 17, 1991

1 Introduction

With the growing complexity of field programmable gate arrays (FPGA), there is the growing need for sophisticated design tools to provide higher level abstractions for managing large designs. However, it is not enough to be able to create large designs. It is also necessary to test and debug them. Debugging FPGA, designs on the circuit board is an awkward task, since the designer can only access the input/output pins of the chip. XS (pronounced as excess") provides the designer with the ability to simulate and debug circuit designs quickly, and with access to all internal nets. XS is a unit-delay, event-driven simulator written in gnu g++ v.1.39. It was designed with an object-oriented methodology, and should be easily adaptable and extensible to any discrete-time simulations.

XS works in conjunction with several other programs to provide an environment for developing FPGA circuits. XDP is an interactive schematic capture program created by Carl Ebeling which supports hierarchical objects, and recursive and repetitive object definitions. xnfwirec is a dependency-checking program which compiles an XDP .dp drawing file into a XILINX Netlist File (XNF). xnfwirec first converts the drawing into a wirec .wc file with the program dp2wc. Next, the conversion program wc2cc converts the .wc file into a C++ .cc file. Finally, this file is linked with a library that will allow the resulting compiled C++ program to output the .xnf file. The exact same process is used for generating a simulation output file graph.rnl, except that a different library is used in the final linking step. The output of the simulator, graph.rnl, is a complete simulation run which can be viewed with the program sigview.

Section 2 describes all of the available commands and features of the simulator. Section 3 is series of examples demonstrating the use of the simulator. Some runtime performance figures are given in Section 4. The specific implementation details of the simulator are described in Section 5.

2 Reference

2.1 Overview

Figure 1 shows the process in which a schematic is converted into an executable simulation. The entire process is encapsulated by a dependency-checking program named wirec 1. By linking with the XS simulation library libxs instead of the XNF (Xilinx Netlist File Format) library lcalib, simulation code is produced. The simulator reads command input from a file named test.script, which controls the execution of the simulation. An optional file, .xsinit, can change various default simulation parameters (such as the file to direct output to). When a simulation is run, the results are placed in a file named graph.rnl. The program sigview may be used to view the results of the simulation.
1Refer to the Xnf-Wirec Tutorial for more information