Multi-sourceable I/O Cell Library: 0.8m Roads Rel 2.1 1- 8 1/31/95

Buffered Clock Driver Pad X08BUF

Delay Information

Path Timing
best, 5.5V, -55C, load:5.2pF tr:0.584ns, tf:0.638ns
typical, 5V, 25C, load:5.2pF tr:1.15ns, tf:1.12ns
worst, 4.5V, 125C, load:5.2pF tr:2.78ns, tf:2.27ns
0.25 * load 1 * load 4 * load 0.25 * load 1 * load 4 * load 0.25 * load 1 * load 4 * load

pad->out1 10->10 PD 0.160 0.194 0.262 0.610 0.651 0.783 1.76 1.85 2.10 0.158 + 0.00504 * CL 0.604 + 0.00870 * CL 1.75 + 0.0176 * CL TR 0.0505 0.0759 0.228 0.100 0.160 0.379 0.237 0.315 0.739

pad->out1 01->01 PD 0.233 0.262 0.295 0.628 0.666 0.779 1.59 1.68 1.99 0.234 + 0.00298 * CL 0.622 + 0.00761 * CL 1.57 + 0.0207 * CL TR 0.0581 0.0759 0.171 0.121 0.167 0.380 0.245 0.365 0.984

Logic Symbol

Size

271.2m x 400m

Pin Capacitance (fF)

pin best typical worst PAD 72.6 96.4 120. OUT1 853. 1240 1660

Input Switch Points (volts) at T= 25?C, VDD = 5 Volts

best worst

VIL 2.65 2.28 VIH 2.66 2.34

PAD OUT

Functional Diagram

Function Table

Logic Equations

OUT = PAD

PAD OUT

PAD OUT

1