Revision 4.0A CMOSN Cell Library: 1.0m 8/27/96 1- 147

1.0 MICRON N-CHANNEL OUTPUT PAD NBUF12

Table 2: Extreme Delay Equations at T = 25 ?C, VDD = 5 Volts, best case trf = 0.6 ns, worst case trf = 1.2 ns

Path Spec. Delay Equation (ns)

Min Max

IN1 fi PAD pdhl 0.144 + 0.0439 ? CL 0.486 + 0.0896 ? CL

Logic Symbol

Size

339l x 550l

1.0m: 169.5m x 275m

Table 1: Pin Capacitance (pF)

Pin Min Max

IN1 0.364 0.386 PAD 0.449 0.483

PAD

IN1

Functional Diagram

Function Table

IN1

VDD

VSS

PAD

IN1 PAD

1 HI-Z

Note: Assuming worst case processing parameters @ T = 125?C, VDD = 4.5 volts,

IOL (@ VOL = 0.4 volts) = 19.8mA