page 1  (5 pages) 2

Page 5

\$7.13

Here instruction miss could happen even if data miss occurs. The resulting total miss = instruction miss + data miss * 0.5

Instr Miss Cycles Data Miss Cycle Total Miss Cycles Cache Miss Penalty Per Instruction Per Data Ref Per Instruction ------------------------------------------------------------------------------ C1 6+1=7 0.04 * 7 = 0.28 0.08*7=0.56 0.56 C2 6+4=10 0.02 * 10=0.2 0.05*10=0.5 0.45 C3 6+4=10 0.02 * 10=0.20 0.04*10=0.40 0.40 ------------------------------------------------------------------------------ Conclusion: C3 spents the least time on misses and C1 spends the most.

\$7.15

I did not take into account the time to send the address, since the problem did not specify, if you assume it to be 1 cycle, it is OK.

Time for scheme 1 is
10*16+16*1 = 176 cycles
Time for scheme 2 is
10*4 + 4*1 = 44 cycles
Time for scheme 3 is
10*4 + 4 * 4 = 56 cycles

\$7.16

New CPI = CPI + Miss penalty * Average Miss Rate For scheme 1: New CPI = 1.2 + 176 * 0.005 = 2.08 For scheme 2: New CPI = 1.2 + 44 * 0.005 = 1.42 For scheme 3: New CPI = 1.2 + 56 * 0.005 = 1.48

Since the clock rate is the same for all three machines, we have

Processor of case 2 is 2.08/1.42 = 1.46 times as fast as that of case 1 Processor of case 2 is 1.48/1.42 = 1.04 times as fast as that of case 3

\$7.22

Execution Time(ET)=Clock cycle*Instruction Count*(CPI+Miss cycles per instr)

EToriginal = 10 * IC * (CPI + 1.5*20*0.05) =10*IC * (CPI +1.5)
= 10*IC*CPI+15IC
= (10CPI+15)IC = 35IC
Etnew = 12*IC*(CPI + 1.5*20*0.03)
= 12*IC*(CPI+0.9)
=24IC+10.8IC=34.8IC

Hence the original machine is slower. However, the performances are very close. The cost is that we doubled the cache size, so it is not worthwhile.