in Proceedings of IEEE International Conference on Computer Design (ICCD'97)

A Comparative Evaluation of Hierarchical Network Architecture of

the HP-Convex Exemplar ?

Robert Casta~neda
Division of Computer Science
The University of Texas at San Antonio
San Antonio, Texas 78249

Xiaodong Zhang
Department of Computer Science
College of William and Mary
Williamsburg, Virginia 23187

James M. Hoover Jr.
Tech NOW Inc.
San Antonio, Texas 78228

Abstract

The Convex Exemplar (SPP1000 and SPP2000 series) is a new commercial distributed shared-memory architecture. Using a set of system kernels and two application programs, we examine performance effects on network latency, hot spot contention, cache coherence and overall scaling capability, which result both from the choice of the network structure as well as from its CC-NUMA memory system feature. Since the KSR-1 was also targeted at scalable cache coherent shared-memory systems by using hierarchical interconnection networks, we compared the architecture and performance results with the KSR-1. Our experiments indicate that the memory access latency of the Exemplar is comparatively low due to its fast processor node and the unique network/system structure. In addition, the Coherent Torodial Interconnect (CTI) rings are efficient in handling cache coherence activities on the Exemplar. However, the Exemplar synchronization primitives need further exploit its hierarchical architecture in a high ?This work is supported in part by the National Science Foundation under research grants CCR-9102854 and CCR-9400719, by the U.S. Air Force Office of Scientific Research under grant AFOSR-95-1-0215, and by a Fellowship from the Southwestern Bell Foundation. Part of the experiments were conducted on the KSR-1 machines at Cornell University and at the University of Washington, and on the Exemplar at HP-Convex Technology Center in Richardson, Texas.