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1 Introduction

Recent advances in the optical fiber technology and VLSI have created new opportunities for research in the area of network communications. With very high{ speed fiber links and VLSI processors, it is feasible to build wide area networks with bandwidths on the order of 100 Mbps or more. Along with these advances, there has been considerable growth in the number and nature of applications (such as packet voice/video, distributed data and transaction processing) that demand high performance communications over long distances. Unfortunately, communication protocol and transport architectures used in conventional packet switched networks have not kept pace with these advances and, therefore, cannot cope with the demands made by both the underlying hardware and higher level applications.

The focus of the Multiswitch project [CSY88] at Purdue is on developing novel hardware and software architectures to provide high performance communications in a wide area network. We are exploring a new, multiprocessor{ based packet switch architecture to build a backbone network with a capacity of 100Mbps or more.

Traditionally, packet switched networks offer a connectionless, datagram service. To the upper layers, lower layer offers a best effort delivery abstraction [Nar88]. A best{effort delivery system does not guarantee to deliver messages; messages may be duplicated, or delivered out of order. Each packet switch has a finite buffer capacity and, in the presence of overloading conditions, it simply discards the packets it cannot handle.

Higher level protocols use datagram mechanism to offer high{level abstractions such as reliable byte streams [Pos81] and request{reply message transac-