This paper presents an efficient technique for estimating the propagation delay of signals in SRAM- based FPGAs, by using an analytic model of MOS integrated circuits. The model provides a facility for experimenting to find the effect that different routing structures in SRAM-based FPGAs have on the speed-performance of implemented circuits. To illustrate the applicability of the technique, two examples of its use are provided.
Having been introduced in 1985 by Xilinx, several different types of FPGAs are now commercially available from an assortment of companies. While each manufacturer?s product offers unique features, all FPGAs share some common characteristics, like an array of logic blocks and programmable interconnect resources. A number of technologies are currently used for implementing the programmable elements in the interconnect, including static RAM, EPROM, EEPROM, and anti-fuse. This paper focuses on SRAM technology because it is widely used, being offered in FPGAs manufactured by Xilinx, Altera, AT&T , Atmel and Algotronix.
A key aspect in the design of an FPGA is its routing architecture, which comprises the resources that are used to interconnect the device?s logic blocks. In early FPGAs , the interconnect consisted mostly of short wire segments that spanned the length or width of one logic block. Longer segments could be formed by joining together two or more of these short segments via programmable routing switches. While this approach provides for good utilization of the wire segments in the sense that there are no long segments that might be wasted on short connections, requiring that long connections pass through several switches in series severely impairs speed-performance. This follows because SRAM-based FPGAs normally use passtransistors to implement routing switches and this kind of switch has significant series resistance and parasitic capacitance. To address these issues, more recent
SRAM-based FPGAs include wire segments of various lengths, but research has not yet determined what specific segmentation schemes produce the best results.
A hypothetical SRAM-based FPGA is depicted in Figure 1. The figure shows an FPGA with a twodimensional array of logic blocks, and both horizontal
and vertical routing channels1. Although the figure does not include the details of the interconnection resources, routing switches would exist for two purposes: 1) to connect the pins of the logic blocks to the wire segments in the channels, and 2) to connect one wire segment to another. Two examples of how SRAM cells could be used to control the routing switches in this type of FPGA are illustrated by Figure 2.
Figure 2(a) shows an SRAM cell controlling a sin-
1. While commercial FPGA architectures differ, this paper assumes the general structure shown in Figure 1, without loss of generality.
Figure 1 - A Hypothetical SRAM-based FPGA.
InterconnectionResourcesLogic BlockI/O Cell
Logic Block Resources
Statatic RAM tatic routing
b) transmission gateStatatic RAM tatic cell routing
a) pass-transistor cell routing
Figure 2 - SRAM-based Routing Switches.
a) pass-transistor b) transmission gate
Modelling Routing Delays in SRAM-based FPGAs
Muhammad Khellah, Stephen Brown and Zvonko Vranesic
Department of Electrical and Computer Engineering
University of Toronto
Toronto, Canada M5S 1A4