Intro 1

Introduction

Section 1: Overview

The I/O cells included in this library were designed to replace the I/O cells of previous releases of the CMOSN cell library. A greater variety of input and output pads are now available to provide the IC designer with the tools that are needed to design ICs which will be used in a wide range of operating environments. The following is a list of critical dimensions for the I/O cells where the first width is for all cells except for clock drivers, and the second width is for clock drivers only:

Wire bonding (0.8 micron) Mils Microns
Passivation opening 3.84 97.6
Pad metal2 to next pad metal2 1.07 27.2
Width (min. pitch) 5.34 135.6
Width (for CLK and BUF pads) 10.68 271.2
Height 15.75 400.0

As can be seen from the numbers above, in order to achieve the tighter pitch, the cells have grown in height relative to the previous CMOSN I/O cells. In order fit the physical layout of the cells within the new footprint, another set of power busses has been added (see Figure 1). Of these two ring pairs, the set closest to the bonding site is called the Driver or outer ring. This set provides power to the ESD structures and the large drivers of the output pads. Power and ground are supplied to the Driver ring using the Z08VDD_D and Z08VSS_D pads. The power and ground ring furthest from the bonding site and closest to the chip?s core is called the Core or inner ring. Power and ground are supplied to the Driver ring using the Z08VDD_C and Z08VSS_C pads. The current convention is to physically keep the two power rings separate. This provides one power and ground ring for the large output transistors of the output drivers and the ESD structures of the input pads, both of which can generate substantial noise on the power and ground plane. The other ring supplies the parts of the I/O cells which are less noisy and also supplies the core logic, thereby increasing the noise immunity due of the core due to switching noise in the ring.