may not seem appropriate because the resistance of a MOS transistor is non-linear, but the next subsection (along with Section 3) shows that it is possible to pick a value of resistance that accurately reflects the delay characteristics of the device.
2.1.1 The Resistance of an ON Switch
To determine the resistance of an ON switch, we use the method described in , as follows. One side of the transistor is connected to a DC voltage source that can be varied from zero to five volts and the other side of the device is connected to ground. As the voltage across the switch is increased, the current is measured (using HSPICE) and the resistance is calculated using Ohm?s law. As an example, Figure 5 shows the
results of simulations to measure the ON resistance of an NMOS pass-transistor assumed to be built using a 0.8m BiCMOS technology . Each of the curves in the figure represents a different value of transistor channel width, from 5 microns for the highest curve to 30 microns for the lowest. As the figure shows, the ON resistance is a monotonically increasing non-linear function of the applied voltage. The same experiment was performed for a transmission gate switch and it was found to have a lower ON resistance than the single NMOS pass-transistor, as one would intuitively expect. This is discussed further in Section 3.
2.1.2 The Capacitance of an ON Switch
The capacitance at the source (or drain) of the ON switch can be approximated as follows :
Cdiffusion consists of two parts, called the junction area capacitance and junction sidewall capacitance. Cdiffusion in then defined according to:
where Cja is the junction area capacitance per square and Cjsw is the junction sidewall capacitance per unit length. Note that Cja and Cjsw are functions of the
Figure 5 - Measuring the Resistance of an NMOS Pass-Transistor Switch.
1 2 3 4 5
Con Cd r ai n C so urce( ) Cd i ffu sio n 1
2 Cga t e?+= =
Cd iff us i on Cja ab( )? Cjsw 2a 2b+( )?+=
voltage across the diffusion/substrate junction, but we approximate this by taking the average value. The variables a and b are the dimensions of the diffusion area as illustrated by Figure 4(b). The Cgate term in Equation 1 can be approximated as
where and are the permittivity of vacuum and silicon dioxide respectively, A is the active area of the gate and Tox is the thickness of the thin oxide between the gate and the substrate.
2.2 Modelling an OFF Routing Switch
An OFF switch can be modelled simply as two capacitors, called Coff, separated by an infinitely large resistance. The value of Coff is equal to Cdiffusion as given by Equation 2.
2.3 Modelling a Wire Segment
A wire segment in an FPGA may span the length or width of a single logic block or it may be longer. Since wire segments are implemented as metal lines they have negligible resistance, but their parasitic capacitance can be significant. Thus, a wire segment is modelled as a capacitor, Cws, between the node corresponding to the wire segment and ground. As in the case of the diffusion capacitance (Equation 2), Cws consists of two parts: area and sidewall capacitance, as defined in Equation 4:
Cma and Cmsw are the metal area capacitance per square and the metal sidewall capacitance per unit length, respectively.
Typical values of capacitance as calculated by the above equations are listed in Table 1. The table gives the values of Coff, Cgate, and Con for several values of transistor channel width, assuming an NMOS transistor built in the same 0.8m BiCMOS technology . In addition, the right-most column of Table 1 shows the product of Con with the maximum switch resistance (Ron_max) taken from Figure 5. This column indicates the inherent delay of the switch, and shows that the
5 4.9 7.9 8.8 24.7
10 8.8 15.8 16.7 23.3
15 12.7 23.7 24.6 22.5
20 16.7 31.6 32.5 22.3
25 20.6 39.5 40.4 22.1
30 24.6 47.4 48.3 22.0
Table 1 - Capacitance values for a 0.8u BiCMOS N- Channel Pass-Transistor Switch.
Cgate eo e s i o2?
e o e s i o2
Cw s Cma SegA r ea( ) Cmsw SegPerimete r( )+=