Digital Teaching Aid
 Flip-Flops - Lesson 7
 Lesson Plan
 (introduction...) Introduction RS Flip-Flops D - Flip-Flop (D-FF) JK Flip-Flop (JK-FF)

### D - Flip-Flop (D-FF)

The generation of two signals to drive a Flip-Flop is a disadvantage in many applications. This has led to the D-FF, a circuit that needs only a single data input.

Fig. 7-8: D Flip-Flop, logic circuit and truth table

CLK ® low: D can change without effect on the output

CLK ® high: Q is forced to equal the value of D

Ex: Create a 4 bit data memory with D-latches (D-FF).

Fig. 7-9: Data storage with D-FF

In Fig. 7-9, when the clock goes high, input data is loaded into the Flip-Flops and appears at the output.

Suppose the data input is:

D3 D2 D1 D0 = 1 0 1 0

When the clock goes high this 4 bit word is loaded into the D-latches, resulting in an output of:

Q3 Q2 Q1 Q0 = 1 0 1 0

Flip-Flop switching time

Fig. 7-10: Timing diagram, FF switching time

 tset: Minimum of time that the date bit must be present before the clock edge hits (because of stray capacitance) thold: The data bit has to be hold long enough for the internal transistors to switch. tp: Switching time, diodes and transistors cannot switch states immediately. (some nanoseconds)